The present invention relates generally to integrated circuits. More particularly, the present invention relates to a delay circuit that provides symmetric delay.
Integrated circuits (ICs) typically contain one or more functional logic blocks (FLB), such as a microprocessor, microcontroller, graphics processor, bus interface circuit, input/output (I/O) circuit, memory circuit, and the like. IC""s are typically assembled into packages that are physically and electrically coupled to a substrate such as a printed circuit board (PCB) or a ceramic substrate to form an xe2x80x9celectronic assemblyxe2x80x9d. The xe2x80x9celectronic assemblyxe2x80x9d can be part of an xe2x80x9celectronic systemxe2x80x9d. An xe2x80x9celectronic systemxe2x80x9d is broadly defined herein as any product comprising an xe2x80x9celectronic assemblyxe2x80x9d. Examples of electronic systems include computers (e.g., desktop, laptop, hand-held, server, etc.), wireless communications devices (e.g., cellular phones, cordless phones, pagers, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, MP3 (Motion Picture Experts Group, Audio Layer 3) players, etc.), and the like.
In the field of electronic systems there is an incessant competitive pressure among manufacturers to drive the performance of their equipment up while driving down production costs. This is particularly true regarding the testing of ICs, where each new generation of IC""s must provide increased performance while generally being smaller or more compact in size. IC""s must generally be tested before they are incorporated into an electronic assembly in order to verify that each component of each FLB on the IC functions properly and to verify that the input/output (I/O) circuits of each IC operate correctly within specified timing parameters or timing margins.
In testing IC""s, it is known to employ I/O loopback or switching state (AC) testing, as for example disclosed in Related Inventions Nos. 1 and 2 above. In I/O loopback testing, data is generated by a FLB within the IC and output through the driver or output component of each I/O circuit. Subsequently, the data is received through the receiver or input component of each I/O circuit and conveyed to the FLB to verify that the correct data has been received. In this manner, the IC can verify that the input and output components of each I/O buffer are correctly operating.
It is known to use source synchronous data transfer on busses interconnecting FLB""s within a single IC or within an electronic assembly comprising one or more IC""s. In a source synchronous interface, a receiving I/O buffer captures data based upon a strobe clock that is provided by another FLB or IC device driving the data.
The use of digital delay circuits on IC""s to assist in centering a strobe signal with respect to a data cell is known in the art, such as for example the delay locked loop disclosed in U.S. Pat. No. 5,905,391 assigned to the assignee of the present invention.
In order to capture source synchronous data within an FLB, and in order to test whether source synchronous interfaces are operating properly, it is desirable to be able to vary the delay of a digital delay circuit in order to shift a strobe signal with respect to a data bit cell time.
Further, in order to reduce pattern dependent jitter in circuitry that is used to capture source synchronous data within an FLB, it is desirable that all nodes of the circuitry have a bandwidth higher than the data frequency. However, capacitor nodes in delay cells often have low bandwidth at low bias levels.
In addition, many electronic applications require a delay circuit to provide a symmetric output, wherein the delay in generating a low/high transitioning delay signal, as measured from a time point of reference, is the same as the delay in generating a high/low transitioning delay signal.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a significant need in the art for a delay circuit in which the amount of signal delay can be easily controlled, that can operate at high data or clock speeds, and that can provide a symmetric output.
In addition, there is a significant need in the art for a delay circuit that can support reliable source synchronous signaling and the testing of source synchronous signaling circuitry.